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Part Number 440GR Revision 1.16 - July 19, 2006
440GR
Power PC 440GR Embedded Processor
Features
* PowerPC(R) 440 processor core operating up to 667MHz with 32KB I-cache and D-cache with parity checking. * Selectable processor:bus clock ratios of N:1, N:2. * Dual bridged Processor Local Buses (PLBs) with 64- and 128-bit widths. * Double Data Rate (DDR) Synchronous DRAM (SDRAM) interface operating up to 133MHz with ECC. * DMA support for external peripherals, internal UART and memory. * PCI V2.2 interface (3.3V only). Thirty-two bits at up to 66MHz. * Programmable interrupt controller supports interrupts from a variety of sources. * Programmable General Purpose Timers (GPT).
Preliminary Data Sheet
* Two Ethernet 10/100Mbps half- or full-duplex interfaces. Operational modes supported are MII, RMII, and SMII with packet reject. * Up to four serial ports (16750 compatible UART). * External peripheral bus (16-bit data) for up to six devices with external mastering. * Two IIC interfaces (one with boot parameter read capability). * NAND Flash interface. * SPI interface. * General Purpose I/O (GPIO) interface. * JTAG interface for board level testing. * Boot from PCI memory, NOR Flash on the extrenal peripheral bus, or NAND Flash on the NAND Flash interface. * Available in RoHS compliant lead-free package.
Description
Designed specifically to address high-end embedded applications, the PowerPC 440GR (PPC440GR) provides a high-performance, low- power solution that interfaces to a wide range of peripherals and incorporates on-chip power management features. This chip contains a high-performance RISC processor, DDR SDRAM controller, PCI bus interface, control for external ROM and peripherals, DMA with scatter-gather support, Ethernet ports, serial ports, IIC interfaces, SPI interface, NAND Flash interface, and general purpose I/O. Technology: CMOS Cu-11, 0.13m. Package: 35mm, 456-ball enhanced plastic ball grid array (E-PBGA). Typical power (estimated): Less than 2.5W at 533MHz, 2.3W at 400MHz. Supply voltages required: 3.3V, 2.5V, 1.5V.
AMCC Proprietary
1
Revision 1.16 - July 19, 2006
440GR - PPC440GR Embedded Processor
Preliminary Data Sheet
Contents
Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PowerPC 440 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DDR SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ethernet Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DMA to PLB 64 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Serial Ports (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serial Ports (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serial Peripheral Interface (SPI/SCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 NAND Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 DDR SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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440GR - PPC440GR Embedded Processor
Revision 1.16 - July 19, 2006
Preliminary Data Sheet
Figures
Figure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. PPC440GR Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. 35mm, 456-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4. Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 5. Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 6. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 7. DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 8. DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 9. DDR SDRAM MemClkOut0 and Read Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 10. DDR SDRAM Read Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 11. DDR SDRAM Read Cycle Timing--Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 12. DDR SDRAM Read Cycle Timing--Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 13. DDR SDRAM Read Cycle Timing--Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Tables
Table 1. System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. DCR Address Map (4KB of Device Configuration Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4. Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 5. Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 6. Non-Functional Ball Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 7. Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 10. Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 13. DC Power Supply Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 14. Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 15. Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 16. Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 17. I/O Specifications--All Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 18. I/O Specifications--333MHz to 533MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 19. DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 20. I/O Timing--DDR SDRAM TDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 21. I/O Timing--DDR SDRAM TSK, TSA, and THA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 22. I/O Timing--DDR SDRAM TSD and THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 23. I/O Timing--DDR SDRAM TSIN and TDIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 24. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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Revision 1.16 - July 19, 2006
440GR - PPC440GR Embedded Processor
Preliminary Data Sheet
Ordering and PVR Information
For information on the availability of the following parts, contact your local AMCC sales office.
Product Name PPC440GR PPC440GR Notes:
Order Part Number (see Notes:) PPC440GR-3PBFFFCX PPC440GR-3PBFFFCX
Package 35mm, 456 ball, PBGA 35mm, 456 ball, PBGA
Revision Level A B
PVR Value 0x422218D3 0x422218D4
JTAG ID 0x2A950049 0x2A950049
1. p = Module Package type B = E-PBGA and contains lead. J = E-PBGA and is lead-free (RoHS compliant). 2. b = Chip revision level A = Revision level A (1.0) B = Revision level B (1.1) 3. fff = Processor frequency 333 = 333MHz 400 = 400MHz 533 = 533MHz 667 = 667MHz 4. C = Case temperature range: -40C to +100C for 333MHz, 400MHz, and 533MHz parts -40C to +85C for 667MHz parts 5. x = Shipping package type Z = tape-and-reel Blank = tray
Each part number contains a revision code. This is the die mask revision number and is included in the part number for identification purposes only. The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only). Refer to the PPC440GR User's Manual for details on accessing these registers. Figure 1. Order Part Number Key
PPC440GR-3JB667CZ
Shipping Package AMCC Part Number Grade 3 Reliability Package Case Temperature Range Processor Frequency Revision Level
Note: The example P/N above is lead-free, capable of running at 667 MHz, and is shipped in tape-and-reel packaging.
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AMCC Proprietary
440GR - PPC440GR Embedded Processor
Revision 1.16 - July 19, 2006
Preliminary Data Sheet
Block Diagram
Figure 2. PPC440GR Functional Block Diagram
10 External Interrupts Clock Control Reset Timers MMU UIC
PPC440
Power Mgmt DCRs
Processor Core JTAG 32KB D-Cache Performance Monitor PLB4 (128 bits) Trace 32KB I-Cache
DCR Bus
GPIO
SPI
IIC x2
BSC
UART x4
On-chip Peripheral Bus (OPB)
DMA Controller PLB Bridge DMA Controller
OPB Bridge
GPT
PLB3 (64 bits) Ethernet 10/100 x2 ZMII
MAL
DDR SDRAM Controller 266MHz max - 13-bit addr - 32-bit data
PCI Bridge 66MHz max - 32 bits - 6 devices
External Peripheral Controller
NAND Flash Controller
1 MII or 2 RMII or 2 SMII
66MHz max - 30-bit addr - 16-bit data
The PPC440GR is a system on a chip (SOC) using IBM CoreConnect BusTM Architecture.
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Revision 1.16 - July 19, 2006
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Preliminary Data Sheet
Address Maps
The PPC440GR incorporates two address maps. The first is a fixed processor System Memory Address Map. This address map defines the possible contents of various address regions which the processor can access. The second is the DCR Address Map for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC440GR processor through the use of mtdcr and mfdcr instructions.
Table 1. System Memory Address Map (Sheet 1 of 2)
Function Local Memory1 EBC Sub Function DDR SDRAM Reserved EBC PCI Memory Reserved PCI I/O Reserved PCI I/O Reserved PCI Configuration Registers Reserved PCI Interrupt Ack / Special Cycle Reserved Local Configuration Registers Reserved 0 EEC0 0000 0 EEC0 0008 0 EED0 0000 0 EED0 0004 0 EF40 0000 0 EF40 0040 0 EEC0 0007 0 EECF FFFF 0 EED0 0003 0 EF3F FFFF 0 EF40 003F 0 EF4F FFFF 64B 4B 8B Start Address 0 0000 0000 0 4000 0000 0 8000 0000 0 A000 0000 0 E000 0000 0 E800 0000 0 E801 0000 0 E880 0000 0 EC00 0000 End Address 0 3FFF FFFF 0 7FFF FFFF 0 9FFF FFFF 0 DFFF FFFF 0 E7FF FFFF 0 E800 FFFF 0 E87F FFFF 0 EBFF FFFF 0 EEBF FFFF 56MB 64KB 512MB 1GB Size 1GB
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440GR - PPC440GR Embedded Processor
Revision 1.16 - July 19, 2006
Preliminary Data Sheet
Table 1. System Memory Address Map (Sheet 2 of 2)
Function Reserved General Purpose Timer Reserved UART0 Reserved UART1 Reserved UART2 Reserved UART3 Reserved IIC0 Reserved IIC1 Internal Peripherals Reserved SPI Reserved OPB Arbiter Reserved GPIO0 Controller Reserved GPIO1 Controller Reserved Ethernet PHY ZMII Reserved Ethernet 0 Controller Ethernet 1 Controller Reserved EBC Boot space (EBC Bank 0 and PCI) Notes: 1. DDR SDRAM can be located anywhere in the Local Memory area of the memory map. 2. EBC and PCI are relocatable, but this map reflects the suggested configuration. 0 EF60 0820 0 EF60 0900 0 EF60 0907 0 EF60 0A00 0 EF60 0A40 0 EF60 0B00 0 EF60 0B80 0 EF60 0C00 0 EF60 0C80 0 EF60 0D00 0 EF60 0D10 0 EF60 0E00 0 EF60 0F00 0 EF60 1000 0 F000 0000 0 FFE0 0000 0 EF60 08FF 0 EF60 0906 0 EF60 09FF 0 EF60 0A3F 0 EF60 0AFF 0 EF60 0B7F 0 EF60 0BFF 0 EF60 0C7F 0 EF60 0CFF 0 EF60 0D0F 0 EF60 0DFF 0 EF60 0EFF 0 EF60 0FFF 0 EFFF FFFF 0 FFDF FFFF 0 FFFF FFFF 254MB 2MB 256B 256B 16B 128B 128B 64B 6B Sub Function Start Address 0 EF50 0000 0 EF60 0000 0 EF60 0100 0 EF60 0300 0 EF60 0308 0 EF60 0400 0 EF60 0408 0 EF60 0500 0 EF60 0508 0 EF60 0600 0 EF60 0608 0 EF60 0700 0 EF60 0720 0 EF60 0800 End Address 0 EF5F FFFF 0 EF60 00FF 0 EF60 02FF 0 EF60 0307 0 EF60 03FF 0 EF60 0407 0 EF60 04FF 0 EF60 0507 0 EF60 05FF 0 EF60 0607 0 EF60 06FF 0 EF60 071F 0 EF60 07FF 0 EF60 081F 32B 32B 8B 8B 8B 8B 256B Size
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Revision 1.16 - July 19, 2006
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Preliminary Data Sheet
Table 2. DCR Address Map (4KB of Device Configuration Registers)
Function Total DCR Address Space1 By function: Reserved Clocking Power On Reset System DCRs Memory Controller External Bus Controller Reserved PLB 128 Performance Monitor Reserved PLB 128 to PLB 64 Bridge Out PLB 64 to PLB 128 Bridge In Reserved PLB 64 Arbiter PLB 128 Arbiter PLB 64 to OPB Bridge Out Reserved OPB to PLB 64 Bridge In Power Management Reserved Interrupt Controller 0 Interrupt Controller 1 Clock, Control, and Reset Reserved DMA to PLB 64 Controller Reserved Ethernet MAL Reserved DMA to PLB 128 Controller Reserved Notes: 1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register. One kiloword (1024W) equals 4KB (4096 B). 000 00C 00E 010 012 014 016 018 020 030 040 070 080 090 0A0 0A8 0B0 0B8 0C0 0D0 0E0 0F0 100 140 180 200 300 340 00B 00D 00F 011 013 015 017 01F 02F 03F 06F 08F 08F 09F 0A7 0AF 0B7 0BF 0CF 0DF 0EF 0FF 13F 17F 1FF 2FF 33F 3FF 12W 2W 2W 2W 2W 2W 2W 8W 16W 16W 64W 16W 16W 16W 8W 8W 8W 8W 16W 16W 16W 16W 64W 64W 128W 512W 64W 512W Start Address 000 End Address 3FF Size 1KW (4KB)1
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Revision 1.16 - July 19, 2006
Preliminary Data Sheet
PowerPC 440 Processor Core
The PowerPC 440 processor core is designed for high-end applications: RAID controllers, SAN, iSCSI, routers, switches, printers, set-top boxes, etc. It implements the Book E PowerPC embedded architecture and uses the 128-bit version of IBM's on-chip CoreConnect Bus Architecture. Features include: * Up to 667MHz operation * PowerPC Book E architecture * 32KB I-cache, 32KB D-cache - UTLB Word Wide parity on data and tag address parity with exception force * Three logical regions in D-cache: locked, transient, normal * D-cache full line flush capability * 41-bit virtual address, 36-bit (64GB) physical address * Superscalar, out-of-order execution * 7-stage pipeline * 3 execution pipelines * Dynamic branch prediction * Memory management unit - 64-entry, full associative, unified TLB with optional parity - Separate instruction and data micro-TLBs - Storage attributes for write-through, cache-inhibited, guarded, and big or little endian * Debug facilities - Multiple instruction and data range breakpoints - Data value compare - Single step, branch, and trap events - Non-invasive real-time trace interface * 24 DSP instructions - Single cycle multiply and multiply-accumulate - 32 x 32 integer multiply - 16 x 16 -> 32-bit MAC
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Revision 1.16 - July 19, 2006
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Preliminary Data Sheet
Internal Buses
The PowerPC 440GR features four standard on-chip buses: two Processor Local Buses (PLBs), one On-Chip Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the PCI bridge connect to the PLBs. The primary OPB hosts lower data rate peripherals. The daisy-chained DCR provides a lower bandwidth path for passing status and control information between the processor core and the other on-chip cores. Features include: * PLB 128 (PLB4) - 128-bit implementation of the PLB architecture - Separate and simultaneous read and write data paths - 36-bit address - Simultaneous control, address, and data phases - Four levels of pipelining - Byte-enable capability supporting unaligned transfers - 32- and 64-byte burst transfers - 133MHz, maximum 4.25GB/s (simultaneous read and write) - Processor:bus clock ratios of N:1 and N:2 * PLB 64 (PLB3) - 64-bit implementation of the PLB architecture - 32-bit address - 133MHz (1:1 ratio with PLB 128), maximum 1.1GB/s (no simultaneous read and write) * OPB - 32-bit data path - 32-bit address - 66.66MHz * DCR - 32-bit data path - 10-bit address
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AMCC Proprietary
440GR - PPC440GR Embedded Processor
Revision 1.16 - July 19, 2006
Preliminary Data Sheet
PCI Interface
The PCI interface allows connection of PCI devices to the PowerPC processor and local memory. This interface is designed to Version 2.2 of the PCI Specification and supports 32- bit PCI devices. Reference Specifications: * PowerPC CoreConnect Bus (PLB) Specification Version 3.1 * PCI Specification Version 2.2 * PCI Bus Power Management Interface Specification Version 1.1 Features include: * PCI 2.2 - Frequency to 66MHz - 32-bit bus * PCI Host Bus Bridge or an Adapter Device's PCI interface * Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with an external arbiter * Support for Message Signaled Interrupts * Simple message passing capability * Asynchronous to the PLB * PCI Power Management 1.1 * PCI register set addressable both from on-chip processor and PCI device sides * Ability to boot from PCI bus memory * Error tracking/status * Supports initiation of transfer to the following address spaces: - Single beat I/O reads and writes - Single beat and burst memory reads and writes - Single beat configuration reads and writes (type 0 and type 1) - Single beat special cycles
DDR SDRAM Memory Controller
The Double Data Rate (DDR) SDRAM memory controller supports industry standard discrete devices. Up to four 256MB logical banks are supported in limited configurations. Global memory timings, address and bank sizes, and memory addressing modes are programmable. Features include: * Registered and non-registered industry standard discrete devices * 32-bit memory interface with optional 8-bit ECC (SEC/DED) * Sustainable 1.1GB/s peak bandwidth at 133MHz * SSTL_2 logic * 1 to 4 chip selects * CAS latencies of 2, 2.5 and 3 supported * DDR200/266 support * Page mode accesses (up to eight open pages) with configurable paging policy * Programmable address mapping and timing * Hardware and software initiated self-refresh * Power management (self-refresh, suspend, sleep)
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Preliminary Data Sheet
External Peripheral Bus Controller (EBC)
Features include: * Up to six ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported * Up to 66.66MHz operation * Burst and non-burst devices * 16-bit byte-addressable data bus * 30-bit address * Peripheral Device pacing with external "Ready" * Latch data on Ready, synchronous or asynchronous * Programmable access timing per device - 256 Wait States for non-burst - 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses - Programmable CSon, CSoff relative to address - Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS * Programmable address mapping * External DMA Slave Support * External master interface - Write posting from external master - Read prefetching on PLB for external master reads - Bursting capable from external master - Allows external master access to all non-EBC PLB slaves - External master can control EBC slaves for own access and control
Ethernet Controller Interface
Ethernet support provided by the PPC440GR interfaces to the physical layer but the PHY is not included on the chip: * One to two 10/100 interfaces running in full- and half-duplex modes - One full Media Independent Interface (MII) with 4-bit parallel data transfer - Two Reduced Media Independent Interfaces (RMII) with 2-bit parallel data transfer - Two Serial Media Independent Interfaces (SMII) - Packet reject support
DMA to PLB 64 Controller
This DMA controller provides a DMA interface between the OPB and the 64-bit PLB. Features include: * Supports the following transfers: - Memory-to-memory transfers - Buffered peripheral to memory transfers - Buffered memory to peripheral transfers * Four channels * Scatter/Gather capability for programming multiple DMA operations * 32-byte buffer * 8-, 16-, 32-bit peripheral support (OPB and external) * 32-bit addressing * Address increment or decrement * Supports internal and external peripherals * Support for memory mapped peripherals * Support for peripherals running on slower frequency buses
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Revision 1.16 - July 19, 2006
Preliminary Data Sheet
DMA to PLB 128 Controller
This DMA controller provides a DMA interface dedicated to the 128-bit PLB. Features include: * Support for memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers * Scatter/gather capability * 128-byte buffer with programmable thresholds
Serial Ports (UART)
Features include: * Up to four ports in the following combinations: - One 8-pin - Two 4-pin - One 4-pin and two 2-pin - Four 2-pin * Selectable internal or external serial clock to allow wide range of baud rates * Register compatibility with NS16750 register set * Complete status reporting capability * Fully programmable serial-interface characteristics * Supports DMA using internal DMA function on PLB 64
IIC Bus Interface
Features include: * Two IIC interfaces provided * Support for Philips(R) Semiconductors I2C Specification, dated 1995 * Operation at 100kHz or 400kHz * 8-bit data * 10- or 7-bit address * Slave transmitter and receiver * Master transmitter and receiver * Multiple bus masters * Supports fixed VDD IIC interface * Two independent 4 x 1 byte data buffers * Twelve memory-mapped, fully programmable configuration registers * One programmable interrupt request signal * Provides full management of all IIC bus protocols * Programmable error recovery * Includes an integrated boot-strap controller that is multiplexed with the second IIC interface
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Preliminary Data Sheet
Serial Peripheral Interface (SPI/SCP)
The Serial Peripheral Interface (also known as the Serial Communications Port) is a full-duplex, synchronous, character-oriented (byte) port that allows the exchange of data with other serial devices. The SCP is a master on the serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB. Features include: * Three-wire serial port interface * Full-duplex synchronous operation * SCP bus master * OPB bus slave * Programmable clock rate divider * Clock inversion * Reverse data * Local data loop back for test
NAND Flash Controller
The NAND Flash controller provides a simple interface between the EBC and up to four separate external NAND Flash devices. It provides both direct command, address, and data access to the external device as well as a memory-mapped linear region that generates data accesses. NAND Flash device data appears on the peripheral data bus. Features include: * 1 to 4 banks supported on EBC * Direct Interfacing to: - Discrete NAND Flash devices (up to 4 devices) - SmartMedia Card socket (22-pins) * Device sizes 4MB-256MB supported * (512 + 16)-B or (2K + 64)-B device page sizes supported * Boot-from-NAND: Execute a linear sequence of boot code out of single page of first block (512B) * Support DMA to allow direct, no-processor-intervention block copy from NAND Flash to SDRAM * ECC provides single-bit error correction and double-bit error detection in each 256B of stored data * Chip selects shared with EBC
General Purpose Timers (GPT)
Provides a separate time base counter and additional system timers in addition to those defined in the processor core. Features include: * 32-bit Time Base Counter driven by the OPB bus clock * Seven 32-bit compare timers
General Purpose IO (GPIO) Controller
* Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master accesses. * 64 GPIOs are multiplexed with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. * Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero, tri-stated if output bit is 1).
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440GR - PPC440GR Embedded Processor
Revision 1.16 - July 19, 2006
Preliminary Data Sheet
Universal Interrupt Controller (UIC)
Two Universal Interrupt Controllers (UIC) are employed. They provide control, status, and communications necessary between the external and internal sources of interrupts and the on-chip PowerPC processor.
Note:
Processor specific interrupts (for example, page faults) do not use UIC resources.
Features include: * 10 external interrupts * Edge triggered or level-sensitive * Positive or negative active * Non-critical or critical interrupt to the on-chip processor core * Programmable interrupt priority ordering * Programmable critical interrupt vector for faster vector processing
JTAG
Features include: * IEEE 1149.1 Test Access Port * IBM RISCWatch Debugger support * JTAG Boundary Scan Description Language (BSDL)
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Preliminary Data Sheet
Package Diagram
Figure 3. 35mm, 456-Ball E-PBGA Package
Top View
(R)
PPC440GR
Lot Number Part Number 1YWWBZZZZZ PPC440GR-nprffft
30 TYP
Gold Gate Release Corresponds to A1 Ball Location
Notes: 1. All dimensions are in mm.
2. Package is available in both lead-free (RoHS compliant) and leaded versions.
C 0.20 C 0.25 C 0.35 C
0.20 35.0 31.75 Bottom View
A
AF AD AB Y V T 35.00.2 P M K H F D B B
AE AC AA W U R N L J G E C A 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 0.75 0.15 SOLDERBALL x 456 0.30 s C A s B s 0.15 s C Thermal Balls
1.27 TYP
Mold Compound
PCB Substrate
0.60.1 2.49 REF 2.65 max
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440GR - PPC440GR Embedded Processor
Revision 1.16 - July 19, 2006
Preliminary Data Sheet
Signal Lists
The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and alternate signals in brackets. Multiplexed signals appear alphabetically multiple times in the list--once for each signal name on the ball. The page number listed gives the page in "Signal Functional Description" on page 50 where the signals in the indicated interface group begin. In cases where signals in the same interface group (for example, Ethernet) have different names to distinguish variations in the mode of operation, the names are separated by a comma with the primary mode name appearing first. These signals are listed only once, and appear alphabetically by the primary mode name. Table 3. Signals Listed Alphabetically (Sheet 1 of 24)
Signal Name AGND AVDD BA0 BA1 BankSel0 BankSel1 BankSel2 BankSel3 BusReq[GPIO31] CAS ClkEn DM0 DM1 DM2 DM3 DM8 [DMAAck0]IRQ8[GPIO47] [DMAAck1]IRQ4[GPIO44] [DMAAck2]PerAddr06[GPIO01] [DMAAck3]PerAddr03[GPIO04] [DMAReq0]IRQ7[GPIO46] [DMAReq1]IRQ5[ModeCtrl] [DMAReq2]PerAddr07[GPIO00] [DMAReq3]PerAddr04[GPIO03] DQS0 DQS1 DQS2 DQS3 DQS8 [DrvrInh1]RejectPkt [DrvrInh2]Halt AMCC Proprietary Ball AE17 Power AD17 AF03 DDR SDRAM AF04 R04 R02 DDR SDRAM R01 N01 AA23 J02 AF05 AE05 AD07 J01 L03 AF07 D18 G25 External Slave Peripheral B06 C07 B24 AC12 External Slave Peripheral C08 D08 AD09 AC08 K03 M04 AC06 Y25 System C25 17 56 DDR SDRAM 51 53 53 DDR SDRAM 51 External Master Peripheral DDR SDRAM DDR SDRAM 54 51 51 51 51 57 Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 2 of 24)
Signal Name ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EMCCD, EMC1RxErr[GPIO25][NFRdyBusy] EMCCrS, EMC0CrsDV[GPIO22] EMCDV, EMC1CrsDV[GPIO21][NFREn] EMCMDClk EMCMDIO EMCRxClk EMCRxD0, EMC0RxD0, EMC0RxD[GPIO12] EMCRxD1, EMC0RxD1, EMC1RxD[GPIO13] EMCRxD2, EMC1RxD0[GPIO14] EMCRxD3, EMC1RxD1[GPIO15] EMCRxErr, EMC0RxErr[GPIO20] EMCTxClk, EMCRefClk EMCTxD0, EMC0TxD0, EMC0TxD[GPIO16] EMCTxD1, EMC0TxD1, EMC1TxD[GPIO17] EMCTxD2, EMC1TxD0[GPIO18][NFCLE] EMCTxD3, EMC1TxD1[GPIO19][NFALE] EMCTxEn, EMC0TxEn, EMCSync[GPIO24] EMCTxErr, EMC1TxEn[GPIO23][NFWEn] [EOT0/TC0]IRQ9[GPIO48] [EOT1/TC1]IRQ6[GPIO45] [EOT2/TC2]PerAddr05[GPIO02] [EOT3/TC3]PerAddr02[GPIO05] ExtAck[GPIO30] ExtReq[GPIO27] ExtReset Ball P02 N02 M01 M02 DDR SDRAM N03 N04 L02 M03 AC16 AD15 AF17 AE16 AC18 AF19 AD19 AE20 AD18 Ethernet AC17 AD16 AC15 AD14 AF13 AF14 AC14 AF20 AF18 A19 H23 External Slave Peripheral A05 B04 AA25 AD26 B23 External Master Peripheral External Master Peripheral External Master Peripheral 54 54 54 53 52 51 Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 3 of 24)
Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball A01 A02 A06 A09 A11 A16 A21 A26 B02 B25 B26 C03 C24 D04 D21 D23 E09 E14 E18 F01 F26 J05 J22 J26 L01 L04 L11 L13 L14 L16 L26 M12 M13 Power 57 Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 4 of 24)
Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball M15 M25 N05 N11 N13 N14 N15 N16 P11 P12 P13 P14 P16 P22 R12 R14 R15 T01 T11 T13 T14 T16 T26 V05 V01 V22 AA01 AA26 AB09 AB13 AB18 AC01 AC04 AC07 AC23 Power 57 Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 5 of 24)
Signal Name GND GND GND GND GND GND GND GND GND GND GND GND Ball AD03 AD24 AE01 AE02 AE25 AF01 Power AF06 AF11 AF16 AF21 AF25 AF26 57 Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 6 of 24)
Signal Name [GPIO00]PerAddr07[DMAReq2] [GPIO01]PerAddr06[DMAAck2] [GPIO02]PerAddr05[EOT2/TC2] [GPIO03]PerAddr04[DMAReq3] [GPIO04]PerAddr03[DMAAck3] [GPIO05]PerAddr02[EOT3/TC3] [GPIO06]PerCS1[NFCE1] [GPIO07]PerCS2[NFCE2] [GPIO08]PerCS3[NFCE3] [GPIO09]PerCS4 [GPIO10]PerCS5 [GPIO11]PerErr [GPIO12]EMCRxD0, EMC0RxD0, EMC0RxD [GPIO13]EMCRxD1, EMC0RxD1, EMC1RxD [GPIO14]EMCRxD2, EMC1RxD0 [GPIO15]EMCRxD3, EMC1RxD1 [GPIO16]EMCTxD0, EMC0TxD0, EMC0TxD [GPIO17]EMCTxD1, EMC0TxD1, EMC1TxD [GPIO18]EMCTxD2, EMC1TxD0[NFCLE] [GPIO19]EMCTxD3, EMC1TxD1[NFALE] [GPIO20]EMCRxErr, EMC0RxErr [GPIO21]EMCDV, EMC1CrsDV[NFREn] [GPIO22]EMCCrS, EMC0CrsDV [GPIO23]EMCTxErr, EMC1TxEn[NFWEn] [GPIO24]EMCTxEn, EMC0TxEn, EMCSync [GPIO25]EMCCD, EMC1RxErr[NFRdyBusy] GPIO26 [GPIO27]ExtReq GPIO28 [GPIO29]HoldAck [GPIO30]ExtAck [GPIO31]BusReq Ball C08 B06 A05 D08 C07 B04 C06 A04 B07 B10 A10 E04 AD19 AE20 AD18 AC17 System AD14 AF13 AF14 AC14 AD16 AF17 AD15 AF18 AF20 AC16 AC26 AD26 Y24 AB25 AA25 AA23 56 Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 7 of 24)
Signal Name GPIO32 GPIO33 [GPIO34]UART0_DCD/UART1_CTS/UART2_Tx [GPIO35]UART0_DSR/UART1_RTS/UART2_Rx [GPIO36]UART0_CTS/UART3_Rx [GPIO37]UART0_RTS/UART3_Tx [GPIO38]UART0_DTR/UART1_Tx [GPIO39]UART0_RI/UART1_Rx [GPIO40]IRQ0 [GPIO41]IRQ1 [GPIO42]IRQ2 [GPIO43]IRQ3 [GPIO44]IRQ4[DMAAck1] [GPIO45]IRQ6[EOT1/TC1] [GPIO46]IRQ7[DMAReq0] [GPIO47]IRQ8[DMAAck0] [GPIO48]IRQ9[EOT0/TC0] [GPIO49]TrcBS0 [GPIO50]TrcBS1 [GPIO51]TrcBS2 [GPIO52]TrcES0 [GPIO53]TrcES1 [GPIO54]TrcES2 [GPIO55]TrcES3 [GPIO56]TrcES4 [GPIO57]TrcTS0 [GPIO58]TrcTS1 [GPIO59]TrcTS2 [GPIO60]TrcTS3 [GPIO61]TrcTS4 [GPIO62]TrcTS5 [GPIO63]TrcTS6 Halt[DrvrInh2] HoldAck[GPIO29] HoldPri[LeakTest] HoldReq[RcvrInh] IIC0SClk IIC0SData Ball W24 AB26 R25 U26 V26 R26 N24 P24 D03 G04 F02 G02 G25 H23 B24 D18 System A19 AE21 AC25 AA24 Y03 AA04 AB03 AB04 AF22 AC22 AE24 AD04 AD06 AC09 AD12 AE15 C25 AB25 V24 Y23 U25 IIC0 Peripheral T24 54 External Master Peripheral 54 System 56 56 Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 8 of 24)
Signal Name [IIC1SClk]SCPClkOut [IIC1SData]SCPDI IRQ0[GPIO40] IRQ1[GPIO41] IRQ2[GPIO42] IRQ3[GPIO43] IRQ4[GPIO44][DMAAck1] IRQ5[ModeCtrl][DMAReq1] IRQ6[GPIO45][EOT1/TC1] IRQ7[GPIO46][DMAReq0] IRQ8[GPIO47][DMAAck0] IRQ9[GPIO48][EOT0/TC0] [LeakTest]HoldPri MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut0 Ball U24 IIC1 Peripheral V25 D03 G04 F02 G02 G25 Interrupts AC12 H23 B24 D18 A19 V24 P01 P04 T02 T04 U01 V02 U04 W03 Y02 AB02 R03 AD01 AD02 AF12 DDR SDRAM AE13 51 DDR SDRAM 51 System 56 55 54 Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 9 of 24)
Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 MemSelfRef [ModeCtrl]IRQ5[DMAReq1] Ball AE12 AD13 AC13 AE11 AF10 AE10 AC11 AF09 AE09 AD10 AF08 AE08 AC10 AE07 AD08 AD05 DDR SDRAM AE03 AC05 AF02 AC03 AC02 AA03 Y04 AA02 V04 Y01 V03 W02 W01 U03 T03 U02 AE04 AC12 DDR SDRAM System 51 56 51 Interface Group Page
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440GR - PPC440GR Embedded Processor
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 10 of 24)
Signal Name [NFALE]EMCTxD3, EMC1TxD1[GPIO19] [NFCE0]PerCS0 [NFCE1]PerCS1[GPIO06] [NFCE2]PerCS2[GPIO07] [NFCE3]PerCS3[GPIO08] [NFCLE]EMCTxD2, EMC1TxD0[GPIO18] [NFRdyBusy]EMCCD, EMC1RxErr[GPIO25] [NFREn]EMCDV, EMC1CrsDV[GPIO21] [NFWEn]EMCTxErr, EMC1TxEn[GPIO23] No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball Ball AC14 D06 C06 A04 B07 AF14 AC16 AF17 AF18 F06 F07 F08 F09 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 G06 G07 G08 G09 G10 G11 G12 G13 G14 G15 A physical ball does not exist at these ball coordinates. NA NAND Flash 55 Interface Group Page
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Revision 1.16 - July 19, 2006
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 11 of 24)
Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball Ball G16 G17 G18 G19 G20 G21 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 J06 J07 J08 J09 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 A physical ball does not exist at these ball coordinates. NA Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 12 of 24)
Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball Ball J20 J21 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 L06 L07 L08 L09 L10 L17 L18 L19 L20 L21 M06 M07 M08 M09 M10 M17 M18 A physical ball does not exist at these ball coordinates. NA Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 13 of 24)
Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball Ball M19 M20 M21 N06 N07 N08 N09 N10 N17 N18 N19 N20 N21 P06 P07 P08 P09 P10 P17 P18 P19 P20 P21 R06 R07 R08 R09 R10 R17 R18 R19 R20 R21 T06 T07 T08 A physical ball does not exist at these ball coordinates. NA Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 14 of 24)
Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball Ball T09 T10 T17 T18 T19 T20 T21 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 V17 A physical ball does not exist at these ball coordinates. NA Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 15 of 24)
Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball Ball V18 V19 V20 V21 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 A physical ball does not exist at these ball coordinates. NA Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 16 of 24)
Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Ball AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 E06 E07 E08 E13 E19 E20 E21 F05 F22 Power G05 G22 H05 H22 L12 L15 M11 M16 N22 57 A physical ball does not exist at these ball coordinates. NA Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 17 of 24)
Signal Name PCIAD00 PCIAD01 PCIAD02 PCIAD03 PCIAD04 PCIAD05 PCIAD06 PCIAD07 PCIAD08 PCIAD09 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 PCIAD28 PCIAD29 PCIAD30 PCIAD31 PCIC0/BE0 PCIC1/BE1 PCIC2/BE2 PCIC3/BE3 PCIClk PCIDevSel PCIFrame Ball B16 C15 D15 A17 B17 A18 C16 D16 C18 A20 C20 B22 A23 A24 C22 D22 PCI H24 F25 J24 K23 K24 J25 L23 K25 K26 M24 M23 L25 N23 N26 M26 P26 B18 F23 PCI F24 E26 B21 D26 G24 PCI PCI PCI 50 50 50 50 50 Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 18 of 24)
Signal Name PCIGnt0/Req PCIGnt1 PCIGnt2 PCIGnt3 PCIGnt4 PCIGnt5 PCIIDSel PCIINT PCIIRDY PCIPar PCIPErr PCIReq0/Gnt PCIReq1 PCIReq2 PCIReq3 PCIReq4 PCIReq5 PCIReset PCISErr PCIStop PCITRDY Ball D17 L24 A25 PCI D25 H25 E24 G26 D20 E25 C23 D24 N25 B20 B19 PCI C19 A22 H26 D19 J23 E23 G23 PCI PCI PCI PCI 50 50 50 50 50 PCI PCI PCI PCI PCI 50 50 50 50 50 50 Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 19 of 24)
Signal Name PerAddr02[GPIO05][EOT3/TC3] PerAddr03[GPIO04][DMAAck3] PerAddr04[GPIO03][DMAReq3] PerAddr05[GPIO02][EOT2/TC2] PerAddr06[GPIO01][DMAAck2] PerAddr07[GPIO00][DMAReq2] PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerBLast PerClk PerCS0[NFCE0] PerCS1[NFCE1][GPIO06] PerCS2[NFCE2][GPIO07] PerCS3[NFCE3][GPIO08] PerCS4[GPIO09] PerCS5[GPIO10] Ball B04 C07 D08 A05 B06 C08 D09 A07 C09 B08 D10 A08 B09 C10 C11 External Slave Peripheral D12 C12 B11 B12 D13 A13 A12 A14 B13 C13 B14 A15 B15 C14 D14 D11 C02 D06 C06 A04 External Slave Peripheral B07 B10 A10 53 External Slave Peripheral External Master Peripheral 53 54 53 Interface Group Page
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440GR - PPC440GR Embedded Processor
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 20 of 24)
Signal Name PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerErr[GPIO11] PerOE PerReady PerR/W PerWBE0 PerWBE1 PSROOut RAS [RcvrInh]HoldReq RefEn RejectPkt[DrvrInh1] Ball H01 K04 G01 J03 J04 H03 E01 G03 External Slave Peripheral H04 E02 D01 F03 C01 F04 E03 B01 E04 B03 C05 D05 H02 External Slave Peripheral C04 C26 K02 Y23 W23 Y25 System DDR SDRAM System System Ethernet 56 51 56 56 52 53 External Master Peripheral External Slave Peripheral External Slave Peripheral External Slave Peripheral 53 53 53 53 53 Interface Group Page
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Revision 1.16 - July 19, 2006
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 21 of 24)
Signal Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SAGND SAVDD SCPClkOut[IIC1SClk] SCPDI[IIC1SData] SCPDO Ball R23 R24 U23 V23 W25 W26 Y26 AB23 AB24 AC20 AC21 AC24 AD20 AD21 AD22 AD23 AE22 AE23 AE26 AF23 AF24 AF15 Power AE14 U24 V25 T23 Serial Peripheral (SPI) 55 57 Other 57 Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 22 of 24)
Signal Name SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVREF1 SVREF2A SVREF2B SysClk SysErr SysReset TCK TDI TDO TestEn TmrClk1 TmrClk2 TMS TrcBS0[GPIO49] TrcBS1[GPIO50] TrcBS2[GPIO51] TrcClk Ball P05 R11 R16 T12 T15 W05 W22 Y05 Y22 Power AA05 AA22 AB06 AB07 AB08 AB14 AB19 AB20 AB21 W04 P03 AE06 AE19 AB01 AE18 B05 C17 C21 A03 AD11 AD25 D02 AE21 AC25 AA24 AC19 Trace 57 Trace 57 System System System JTAG JTAG JTAG System System System JTAG 56 56 56 55 55 55 56 56 56 55 DDR SDRAM 51 57 Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 23 of 24)
Signal Name TrcES0[GPIO52] TrcES1[GPIO53] TrcES2[GPIO54] TrcES3[GPIO55] TrcES4[GPIO56] TrcTS0[GPIO57] TrcTS1[GPIO58] TrcTS2[GPIO59] TrcTS3[GPIO60] TrcTS4[GPIO61] TrcTS5[GPIO62] TrcTS6[GPIO63] TRST UART0_CTS/UART3_Rx[GPIO36] UART0_RTS/UART3_Tx[GPIO37] UART0_Rx UART0_Tx UART0_DCD/UART1_CTS/UART2_Tx[GPIO34] UART0_DSR/UART1_RTS/UART2_Rx[GPIO35] UART0_DTR/UART1_Tx[GPIO38] UART0_RI/UART1_Rx[GPIO39] UARTSerClk Ball Y03 AA04 AB03 AB04 AF22 AC22 AE24 AD04 AD06 AC09 AD12 AE15 D07 V26 R26 T25 P25 R25 U26 N24 P24 P23 UART Peripheral 54 JTAG 55 Trace 57 Trace 57 Interface Group Page
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Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 24 of 24)
Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD WE Ball E05 E10 E11 E12 E15 E16 E17 E22 K05 K22 L05 L22 M05 M22 M14 N12 Power P15 R05 R13 R22 T05 T22 U05 U22 AB05 AB10 AB11 AB12 AB15 AB16 AB17 AB22 K01 DDR SDRAM 51 57 Interface Group Page
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Preliminary Data Sheet
In the following table, only the primary (default) signal name is shown for each pin. Multiplexed or multifunction signals are marked with an asterisk (*). To determine what signals or functions are multiplexed on those pins, look up the primary signal name in Table 3, Signals Listed Alphabetically. Table 4. Signals Listed by Ball Assignment (Sheet 1 of 7)
Ball A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 GND GND TestEn PerCS2* PerAddr05* GND PerAddr09 PerAddr13 GND PerCS5* GND PerAddr23 PerAddr22 PerAddr24 PerAddr28 GND PCIAD03 PCIAD05 IRQ9* PCIAD09 GND PCIReq4 PCIAD12 PCIAD13 PCIGnt2 GND Signal Name Ball B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 Signal Name PerData15 GND PerOE PerAddr02* TCK PerAddr06* PerCS3* PerAddr11 PerAddr14 PerCS4* PerAddr19 PerAddr20 PerAddr25 PerAddr27 PerAddr29 PCIAD00 PCIAD04 PCIC0/BE0 PCIReq2 PCIReq1 PCIClk PCIAD11 ExtReset IRQ7* GND GND Ball C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 Signal Name PerData12 PerClk GND PerWBE1 PerReady PerCS1* PerAddr03* PerAddr07* PerAddr10 PerAddr15 PerAddr16 PerAddr18 PerAddr26 PerAddr30 PCIAD01 PCIAD06 TDI PCIAD08 PCIReq3 PCIAD10 TDO PCIAD14 PCIPar GND Halt* PSROOut Ball D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 Signal Name PerData10 TMS IRQ0* GND PerR/W PerCS0* TRST PerAddr04* PerAddr08 PerAddr12 PerBLast PerAddr17 PerAddr21 PerAddr31 PCIAD02 PCIAD07 PCIGnt0/Req IRQ8* PCIReset PCIINT GND PCIAD15 GND PCIPErr PCIGnt3 PCIDevSel
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440GR - PPC440GR Embedded Processor
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 2 of 7)
Ball E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 Signal Name PerData06 PerData09 PerData14 PerErr* VDD OVDD OVDD OVDD GND VDD VDD VDD OVDD GND VDD VDD VDD GND OVDD OVDD OVDD VDD PCIStop PCIGnt5 PCIIRDY PCIC3/BE3 Ball F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 Signal Name GND IRQ2* PerData11 PerData13 OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD PCIC1/BE1 PCIC2/BE2 PCIAD17 GND Ball G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 Signal Name PerData02 IRQ3* PerData07 IRQ1* OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD PCITRDY PCIFrame IRQ4* PCIIDSel Ball H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 Signal Name PerData00 PerWBE0 PerData05 PerData08 OVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball OVDD IRQ6* PCIAD16 PCIGnt4 PCIReq5
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440GR - PPC440GR Embedded Processor
Revision 1.16 - July 19, 2006
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 3 of 7)
Ball J01 J02 J03 J04 J05 J06 J07 J08 J09 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 DM2 CAS PerData03 PerData04 GND No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball GND PCISErr PCIAD18 PCIAD21 GND Signal Name Ball K01 K02 K03 K04 K05 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 WE RAS DQS2 PerData01 VDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball VDD PCIAD19 PCIAD20 PCIAD23 PCIAD24 Signal Name Ball L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 Signal Name GND ECC6 DM3 GND VDD No ball No ball No ball No ball No ball GND OVDD GND GND OVDD GND No ball No ball No ball No ball No ball VDD PCIAD22 PCIGnt1 PCIAD27 GND Ball M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 Signal Name ECC2 ECC3 ECC7 DQS3 VDD No ball No ball No ball No ball No ball OVDD GND GND VDD GND OVDD No ball No ball No ball No ball No ball VDD PCIAD26 PCIAD25 GND PCIAD30
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Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 4 of 7)
Ball N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 Signal Name BankSel3 ECC1 ECC4 ECC5 GND No ball No ball No ball No ball No ball GND VDD GND GND GND GND No ball No ball No ball No ball No ball OVDD PCIAD28 UART0_DTR* PCIReq0/Gnt PCIAD29 Ball P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 Signal Name MemAddr00 ECC0 SVREF2A MemAddr01 SVDD No ball No ball No ball No ball No ball GND GND GND GND VDD GND No ball No ball No ball No ball No ball GND UARTSerClk UART0_RI* UART0_Tx* PCIAD31 Ball R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 Signal Name BankSel2 BankSel1 MemAddr10 BankSel0 VDD No ball No ball No ball No ball No ball SVDD GND VDD GND GND SVDD No ball No ball No ball No ball No ball VDD Reserved Reserved UART0_DCD* UART0_RTS* Ball T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 GND MemAddr02 MemData30 MemAddr03 VDD No ball No ball No ball No ball No ball GND SVDD GND GND SVDD GND No ball No ball No ball No ball No ball VDD SCPDO IIC0SData UART0_Rx GND Signal Name
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440GR - PPC440GR Embedded Processor
Revision 1.16 - July 19, 2006
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 5 of 7)
Ball U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 Signal Name MemAddr04 MemData31 MemData29 MemAddr06 VDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball VDD Reserved SCPClkOut* IIC0SClk UART0_DSR* Ball V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 GND MemAddr05 MemData26 MemData24 GND No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball GND Reserved HoldPri* SCPDI* UART0_CTS* Signal Name Ball W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 Signal Name MemData28 MemData27 MemAddr07 SVREF1 SVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball SVDD RefEn GPIO32 Reserved Reserved Ball Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Signal Name MemData25 MemAddr08 TrcES0* MemData22 SVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball SVDD HoldReq* GPIO28 RejectPkt* Reserved
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440GR - PPC440GR Embedded Processor
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 6 of 7)
Ball AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 GND MemData23 MemData21 TrcES1* SVDD No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball SVDD BusReq* TrcBS2* ExtAck* GND Signal Name Ball AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 Signal Name SysErr MemAddr09 TrcES2* TrcES3* VDD SVDD SVDD SVDD GND VDD VDD VDD GND SVDD VDD VDD VDD GND SVDD SVDD SVDD VDD Reserved Reserved HoldAck* GPIO33 Ball AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 GND MemData20 MemData19 GND MemData17 DQS8 GND DQS1 TrcTS4* MemData12 MemData06 IRQ5* MemData02 EMCTxD3* EMCTxClk* EMCCD* EMCRxD3* EMCMDIO TrcClk Reserved Reserved TrcTS0* GND Reserved TrcBS1* GPIO26 Signal Name Ball AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 Signal Name MemAddr11 MemAddr12 GND TrcTS2* MemData15 TrcTS3* DM1 MemData14 DQS0 MemData09 TmrClk1 TrcTS5* MemData01 EMCTxD0* EMCCrS* EMCRxErr* AVDD EMCRxD2* EMCRxD0* Reserved Reserved Reserved Reserved GND TmrClk2 ExtReq*
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440GR - PPC440GR Embedded Processor
Revision 1.16 - July 19, 2006
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 7 of 7)
Ball AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 GND GND MemData16 MemSelfRef DM0 SVREF2B MemData13 MemData11 MemData08 MemData05 MemData03 MemData00 MemClkOut0 SAVDD TrcTS6* EMCMDClk AGND SysReset SysClk EMCRxD1* TrcBS0* Reserved Reserved TrcTS1* GND Reserved Signal Name Ball AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Signal Name GND MemData18 BA0 BA1 ClkEn GND DM8 MemData10 MemData07 MemData04 GND MemClkOut0 EMCTxD1* EMCTxD2* SAGND GND EMCDV* EMCTxErr* EMCRxClk EMCTxEn* GND TrcES4* Reserved Reserved GND GND Ball Signal Name Ball Signal Name
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440GR - PPC440GR Embedded Processor
Preliminary Data Sheet
Signal Descriptions
The PPC440GR embedded controller is packaged in a 456-ball enhanced plastic ball grid array (E-PBGA). The following tables describe the package level pinout. Table 5. Pin Summary
Group
Signal pins, non-multiplexed Signal pins, multiplexed Total Signal Pins AVDD SAVDD SAGnd AGnd OVDD SVDD VDD Gnd Total Power Pins Reserved Total Pins
No. of Pins
221 62 283 1 1 1 1 18 18 32 80 152 21 456
In the table "Signal Functional Description" on page 50, each I/O signal is listed along with a short description of its function. Active-low signals (for example, RAS) are marked with an overline. Please see "Signals Listed Alphabetically" on page 17 for the pin (ball) number to which each signal is assigned. Multiplexed Signals Some signals are multiplexed on the same pin so that the pin can be used for different functions. In most cases, the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in "Signals Listed Alphabetically" on page 17. It is expected that in any single application a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. The circuit type for multiplexed signals is shown as "Multiplex." The actual circuit type is the same as the primary signal. Multipurpose Signals In addition to multiplexing, some pins are also multi-purpose. For example, the EBC peripheral controller address pins (PerAddr) are used as outputs by the PPC440GR to broadcast an address to external slave devices when the PPC440GR has control of the external bus. When during the course of normal chip operation an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC440GR. In this example, the pins are also bidirectional, serving both as inputs and outputs.
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440GR - PPC440GR Embedded Processor
Revision 1.16 - July 19, 2006
Preliminary Data Sheet
Multimode Signals In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When a pin has multiple signal names assigned to distinguish different modes of operation, all of the names are shown. Strapping Pins One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see "Strapping" on page 79). Note that these are not multiplexed pins since the function of the pins is not programmable. Reserved Pins The balls marked Reserved on this chip are not functional. However, most of the reserved balls cannot be left unconnected. Connect the balls shown in Table 6 as indicated: Table 6. Non-Functional Ball Connections
Ball
R23 R24 U23 V23 W25 W26 Y26 AB23 AB24 AC20 AC21 AC24 AD20 AD21 AD22 AD23 AE22 AE23 AE26 AF23 AF24
Connection
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND do not connect GND GND do not connect GND
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440GR - PPC440GR Embedded Processor
Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 1 of 8)
Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3k to 3.3V) 3. Must pull down (recommended value is 1k) 4. If not used, must pull up (recommended value is 3k to 3.3V) 5. If not used, must pull down (recommended value is 1k) 6. Strapping input during reset; pull-up or pull-down required
Signal Name PCI Interface PCIAD00:31 PCIC0:3/BE0:3 PCIClk PCIDevSel PCIFrame Address/Data bus (bidirectional). PCI Command/Byte Enables. Provides timing to the PCI interface for PCI transactions. Indicates the driving device has decoded its address as the target of the current access. Driven by the current master to indicate beginning and duration of an access. Indicates that the specified agent is granted access to the bus. When the internal arbiter is enabled, output is PCIGnt0. When the internal arbiter is disabled, output is Req. Indicates that the specified agent is granted access to the bus. Used as a chip select during configuration read and write transactions. Level sensitive PCI interrupt. Indicates initiating agent's ability to complete the current data phase of the transaction. Even parity. Reports data parity errors during all PCI transactions except a Special Cycle. Indicates to the PCI arbiter that the specified agent wishes to use the bus. When the internal arbiter is enabled, input is PCIReq0. When internal arbiter is disabled, input is Gnt. An indication to the PCI arbiter that the specified agent wishes to use the bus. Brings PCI device registers and logic to a consistent state. Reports address parity errors, data parity errors on the Special Cycle command, or other catastrophic system errors. Indicates the current target is requesting the master to stop the current transaction. I/O I/O I I/O I/O 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI Description I/O Type
Notes
PCIGnt1/Req PCIGnt2:6 PCIIDSel PCIINT PCIIRDY PCIPar PCIPErr
O O I O I/O I/O I/O
3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI
PCIReq0/Gnt
I
3.3V PCI
PCIReq1:5 PCIReset PCISErr PCIStop PCITRDY
I O I/O I/O I/O
3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI
Indicates the target agent's ability to complete the current data phase of the transaction.
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440GR - PPC440GR Embedded Processor
Revision 1.16 - July 19, 2006
Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 2 of 8)
Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3k to 3.3V) 3. Must pull down (recommended value is 1k) 4. If not used, must pull up (recommended value is 3k to 3.3V) 5. If not used, must pull down (recommended value is 1k) 6. Strapping input during reset; pull-up or pull-down required
Signal Name DDR SDRAM Interface BA0:1 BankSel0:3 CAS ClkEn DM0:3 DM8 DQS0:3 DQS8 ECC0:7 MemAddr00:12 MemClkOut0 MemClkOut0 MemData00:31 MemSelfRef RAS WE SVREF1 SVREF2A:B Bank Address supporting up to four internal banks. Selects up to four external DDR SDRAM banks. Column Address Strobe. Clock Enable. Memory write data byte lane masks. DM8 is the byte lane mask for the ECC byte lane. Byte lane data strobe. DQS8 is the data strobe for the ECC byte lane. ECC check bits 0:7. Memory address bus. Subsystem clock. Memory data bus. Self refresh. Row Address Strobe. Write Enable. SSTL reference voltage. Supplemental SSTL reference voltage. O O O O O I/O I/O O O I/O I O O I I 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 Diff driver 2.5V SSTL_2 3.3V tolerant 2.5V CMOS 2.5V SSTL_2 2.5V SSTL_2 Volt ref receiver Volt ref pin (supplemental) 5 Description I/O Type
Notes
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440GR - PPC440GR Embedded Processor
Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 3 of 8)
Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3k to 3.3V) 3. Must pull down (recommended value is 1k) 4. If not used, must pull up (recommended value is 3k to 3.3V) 5. If not used, must pull down (recommended value is 1k) 6. Strapping input during reset; pull-up or pull-down required
Signal Name Ethernet Interface EMCCD, EMC1RxErr EMCCrS, EMC0CrsDV EMCDV, EMC1CrsDV EMCMDClk EMCMDIO EMCRxClk EMCRxD0:1, EMC0RxD0:1 EMC0:BRxD EMCRxD2:3, EMC1RxD0:1 EMCRxErr, EMC0RxErr EMCTxClk, EMCRefClk EMCTxD0:1, EMC0TxD0:1 EMC0:BTxD EMCTxD2:3, EMC1TxD0:1 EMCTxEn, EMC0TxEn, EMCSync EMCTxErr, EMC1TxEn RejectPkt MII: Collision detection. RMII B: Receive error. MII: Carrier sense. RMII A: Carrier sense data valid. MII: Data valid. RMII B: Carrier sense data valid. MII: Management data clock. MII: Transfer command and status information between MII and PHY. MII: Receive clock. MII: Receive data. RMII A: Receive data. SMII A and B: Receive data. MII: Receive data. RMII B: Receive data. MII: Receive error. RMII A: Receive error. MII: Transmit clock. RMII and SMII: Transmit clock (max 125MHz in SMII). MII: Transmit data. RMII A: Transmit data. SMII A and B: Transmit data. MII: Transmit data. RMII B: Transmit data. MII: Transmit data enabled. RMII A: Transmit data enabled. SMII: Sync signal. MII: Transmit error. RMII B: Transmit data enabled. External request to reject a packet. I/O I/O I/O O I/O I/O 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 5 Description I/O Type
Notes
I/O
I/O I/O I
I/O
I/O
O
I/O I
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440GR - PPC440GR Embedded Processor
Revision 1.16 - July 19, 2006
Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 4 of 8)
Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3k to 3.3V) 3. Must pull down (recommended value is 1k) 4. If not used, must pull up (recommended value is 3k to 3.3V) 5. If not used, must pull down (recommended value is 1k) 6. Strapping input during reset; pull-up or pull-down required
Signal Name External Slave Peripheral Interface DMAAck0:3 DMAReq0:3 EOT0:3/TC0:3 PerAddr02:07 PerAddr08:31 Used by the PPC440GR to indicate that data transfers have occurred. Used by slave peripherals to indicate they are prepared to transfer data. End Of Transfer/Terminal Count. Peripheral address bus used by PPC440GR when not in external master mode, otherwise used by external master. Peripheral address bus used by PPC440GR when not in external master mode, otherwise used by external master. Used by either the peripheral controller, DMA controller, or external master to indicates the last transfer of a memory access. External peripheral device select. Peripheral data bus used by PPC440GR when not in external master mode, otherwise used by external master. Note: PerData00 is the most significant bit (msb) on this bus. Used by either peripheral controller or DMA controller depending upon the type of transfer involved. When the PPC440GR is the bus master, it enables the selected device to drive the bus. Used by a peripheral slave to indicate it is ready to transfer data. Used by the PPC440GR when not in external master mode, as output by either the peripheral controller or DMA controller depending upon the type of transfer involved. High indicates a read from memory, low indicates a write to memory. Otherwise, it used by the external master as an input to indicate the direction of transfer. External peripheral data bus byte enables. External Error. Used as an input to record external slave peripheral errors. O I I/O I/O I/O Multiplex Multiplex Multiplex 3.3V LVTTL 3.3V LVTTL 1, 5 1, 5 1, 2 Description I/O Type
Notes
PerBLast PerCS0:5 PerData00:15
I/O O I/O
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
1, 4 2 1
PerOE
O
3.3V LVTTL
2
PerReady
I
3.3V LVTTL
PerR/W
I/O
3.3V LVTTL
1, 2
PerWBE0:1 PerErr
I/O I/O
3.3V LVTTL 3.3V LVTTL
1, 2 1, 5
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Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 5 of 8)
Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3k to 3.3V) 3. Must pull down (recommended value is 1k) 4. If not used, must pull up (recommended value is 3k to 3.3V) 5. If not used, must pull down (recommended value is 1k) 6. Strapping input during reset; pull-up or pull-down required
Signal Name External Master Peripheral Interface BusReq ExtAck ExtReq ExtReset HoldAck HoldReq HoldPri PerClk UART Peripheral Interface UARTSerClk UARTn_Rx UARTn_Tx UARTn_DCD UARTn_DSR UARTn_CTS UARTn_DTR UARTn_RTS UARTn_RI IIC Peripheral Interface IIC0SClk IIC0SData IIC10SClk IIC1SData IIC0 Serial Clock. IIC0 Serial Data. IIC1 Serial Clock. IIC1 Serial Data. I/O I/O I/O I/O 3.3V LVTTL 3.3V LVTTL Multiplex Multiplex 1, 2 1, 2 Serial clock input that provides an alternative to the internally generated serial clock. Used in cases where the allowable internally generated clock rates are not satisfactory. UART Receive data. UART Transmit data. UART Data Carrier Detect. UART Data Set Ready. UART Clear To Send. UART Data Terminal Ready. UART Request To Send. UART Ring Indicator. I I O I I I O O I 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 1, 4 1, 4 4 6 6 1, 4, 6 4 4 1, 4 Bus Request. Used when the PPC440GR needs to regain control of peripheral interface from an external master. External Acknowledgement. Used by the PPC440GR to indicate that a data transfer occurred. External Request. Used by an external master to indicate it is prepared to transfer data. Peripheral Reset. Used by an external master and by synchronous peripheral slaves. Hold Acknowledge. Used by the PPC440GR to transfer ownership of peripheral bus to an external master. Hold Request. Used by an external master to request ownership of the peripheral bus. Hold Primary. Used by an external master to indicate the priority of a given external master tenure. Peripheral Clock. Used by an external master and by synchronous peripheral slaves. O O I O O I I O Multiplex Multiplex Multiplex 3.3V LVTTL Multiplex Multiplex Multiplex 3.3V LVTTL 1, 5 1, 4 Description I/O Type
Notes
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Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 6 of 8)
Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3k to 3.3V) 3. Must pull down (recommended value is 1k) 4. If not used, must pull up (recommended value is 3k to 3.3V) 5. If not used, must pull down (recommended value is 1k) 6. Strapping input during reset; pull-up or pull-down required
Signal Name NAND Flash Interface NFALE NFCE0:3 NFCLE NFRdyBusy NFREn NFWEn Serial Peripheral Interface Clock output. SCPClkOut, the serial port master clock out, is used to synchronize all data movement both into and out of the device through the serial data ports. Normally, data is shifted out on the rising edge of the clock and shifted in on the negative edge. SCPClkOut is also used to shift data into and out of the slave device. When the SPMODE register is reset, SCPClkOut is forced to 0. Data In. Data is received from the connected slave device and is captured synchronously with SysClk. Data output. Data is sent to the connected slave device synchronously with SysClk. Address Latch Enable. Chip Enable (multiplexed with the PerCS0:3 signals). Command Latch Enable. Ready/Busy. Indicates status of device during program erase or page read. This signal is wire-or connected from all NAND Flash devices. Read Enable strobe. Write Enable strobe. O O O I O O Multiplex Multiplex Multiplex Multiplex Multiplex Multiplex Description I/O Type
Notes
SCPClkOut
O
3.3V LVTTL
SCPDI
I
3.3V LVTTL
SCPDO Interrupts Interface IRQ0:4 IRQ5 IRQ6:9 JTAG Interface TCK TDI TDO TMS TRST
O
3.3V LVTTL
External interrupt requests 0 through 4. External interrupt request 5. External interrupt requests 6 through 9.
I/O I I/O
3.3V LVTTL 3.3V tolerant 2.5V CMOS 3.3V LVTTL
1, 5 1, 5 1, 5
Test Clock. Test Data In. Test Data Out. Test Mode Select. Test Reset.
I I O I I
3.3V LVTTL w/pull-up 3.3V LVTTL w/pull-up 3.3V LVTTL 3.3V LVTTL w/pull-up 3.3V LVTTL w/pull-up
1 4
1 5
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Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 7 of 8)
Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3k to 3.3V) 3. Must pull down (recommended value is 1k) 4. If not used, must pull up (recommended value is 3k to 3.3V) 5. If not used, must pull down (recommended value is 1k) 6. Strapping input during reset; pull-up or pull-down required
Signal Name System Interface SysClk SysErr Main system clock input. Set to 1 when a machine check is generated. Main system reset. External logic can drive this bidirectional pin low (minimum of 16 cycles) to initiate a system reset. A system reset can also be initiated by software. Implemented as an open-drain output (two states; 0 or open circuit). Halt from external debugger. Processor timer external input clock. This signal must be connected to a clock. It can be connected to any available clocking signal in the frequency range of 32kHz to 100MHz including TmrClk1. General purpose I/O 0 through 63. To access these functions, software must set DCR register bits. Test Enable. Receiver Inhibit. Active only when TestEn is active. Mode Control. Leakage Test. Reference Enable. Driver Inhibit. Used for test purposes only. Tie up as specified in Note 2 for normal operation. Module characterization and screening. Clock O 3.3V LVTTL 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V LVTTL 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS Multiplex Multiplex Multiplex Multiplex Multiplex Multiplex 3.3V tolerant 2.5V CMOS Perf screen ring osc 2 1, 3 3 Description I/O Type
Notes
SysReset
I/O
1, 2
Halt TmrClk1
I I
1, 4
TmrClk2
I
GPIO00:63 TestEn RcvrInh ModeCtrl LeakTest RefEn DrvrInh1:2 PSROOut
I/O I I I I I I O
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Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 8 of 8)
Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3k to 3.3V) 3. Must pull down (recommended value is 1k) 4. If not used, must pull up (recommended value is 3k to 3.3V) 5. If not used, must pull down (recommended value is 1k) 6. Strapping input during reset; pull-up or pull-down required
Signal Name Trace Interface TrcBS0:2 TrcClk TrcES0:4 TrcTS0:6 Power VDD OVDD SVDD GND AVDD AGND SAVDD SAGND Other Reserved To avoid noise pickup problems, most of these balls must be connected in the board design as shown Table 6 on page 49. na na 1.5V supply--Logic voltage. 3.3V supply--I/O (except DDR SDRAM, Ethernet). 2.5V supply--SDRAM, Ethernet. Ground. 1.5V--Filtered voltage for system PLLs (analog). PLL (analog) voltage ground. 1.5V--Filtered voltage for memory PLL (analog). PLL (analog) memory voltage ground. na na na na na na na na na na na na na na na na Trace branch execution status. Trace data capture clock, runs at 1/4 the frequency of the processor. Trace Execution Status is presented every fourth processor clock cycle. Additional information on trace execution and branch status. I/O O I/O I/O 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOSL 3.3V LVTTL 3.3V tolerant 2.5V CMOS Description I/O Type
Notes
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Device Characteristics
Table 8. Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device. None of the performance specification contained in this document are guaranteed when operating at these maximum ratings.
Characteristic Supply Voltage (Internal Logic) Supply Voltage (I/O, except SDRAM, Ethernet) Supply Voltage (SDRAM, Ethernet) PLL Supply Voltage SDRAM PLL Supply Voltage Input Voltage (3.3V LVTTL receivers) Storage Temperature Range Case temperature under bias Notes: 1. If OVDD 0.4V, it is required that VDD 0.4V. Supply excursions not meeting this criteria must be limited to less than 25ms duration during each power up or power down event. 2. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440GR. A separate filter, as shown below, is recommended for each voltage: VDD L L - SMT ferrite bead chip, Murata BLM31A700S AVDD, SAVDD Symbol VDD OVDD SVDD AVDD SAVDD VIN TSTG TC Value 0 to +1.65 0 to +3.6 0 to +2.7 0 to +1.65 0 to +1.65 0 to +3.6 -55 to +150 -40 to +120 Unit V V V V V V C C 3 2 2 Notes 1 1
C
C - 0.1F ceramic 3. This value is not a specification of the operational temperature range, it is a stress rating only.
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Preliminary Data Sheet
Table 9. Recommended DC Operating Conditions (Sheet 1 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability.
Parameter Logic Supply Voltage I/O Supply Voltage SDRAM Supply Voltage PLL Supply Voltages SDRAM PLL Voltage DDR SDRAM Reference Voltage Input Logic High (2.5V SSTL) Input Logic High (2.5V CMOS, 3.3V tolerant receiver)
Symbol VDD OVDD SVDD AVDD SAVDD SVREF
Minimum +1.4 +3.0 +2.3 +1.4 +1.4 +1.15 SVREF+0.18 1.7
Typical +1.5 +3.3 +2.5 +1.5 +1.5 +1.25
Maximum +1.6 +3.6 +2.7 +1.6 +1.6 +1.35 SVDD+0.3 ??? OVDD+0.5 +3.6 SVREF-0.18 0.7 0.35OVDD +0.8 SVDD ??? OVDD OVDD 0.55 0.4
Unit V V V V V V V V V V V V V V V V V V V V V V
Notes 4 4 4 3, 4 3, 4 2
VIH Input Logic High (3.3V PCI) Input Logic High (3.3V LVTTL) Input Logic Low (2.5V SSTL) Input Logic Low (2.5V CMOS, 3.3V tolerant receiver) VIL Input Logic Low (3.3V PCI) Input Logic Low (3.3V LVTTL) Output Logic High (2.5V SSTL) Output Logic High (2.5V CMOS, 3.3V tolerant receiver) VOH Output Logic High (3.3V PCI) Output Logic High (3.3V LVTTL) Output Logic Low (2.5V SSTL) Output Logic Low (2.5V CMOS, 3.3V tolerant receiver) VOL Output Logic Low (3.3V PCI) Output Logic Low (3.3V LVTTL) Input Leakage Current (No pull-up or pull-down) Input Leakage Current for Pull-Down Input Leakage Current for Pull-Up Input Max Allowable Overshoot (3.3V LVTTL) Input Max Allowable Undershoot (3.3V LVTTL) Output Max Allowable Overshoot (3.3V LVTTL) Output Max Allowable Undershoot (3.3V LVTTL) IIL1 IIL2 IIL3 VIMAO VIMAU VOMAO VOMAU3 -0.6 -0.6 +3.9 0 0 0 (LPDL) -150 (LPDL) -0.5 0 +1.95 2.0 0.9OVDD +2.4 0 1 0.5OVDD +2.0 -0.3 ??? 1
1
0.1OVDD +0.4 0 200 (MPUL) 0 (MPUL) +3.9
1
A A A
V V V V
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Preliminary Data Sheet
Table 9. Recommended DC Operating Conditions (Sheet 2 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability.
Parameter Case Temperature: 333MHz, 400MHz, and 533MHz parts 667MHz parts Notes:
Symbol
Minimum -40 -40
Typical
Maximum +100 +85
Unit
Notes
TC
C
1. PCI drivers meet PCI specifications. 2. SVREF = SVDD/2 3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440GR. See "Absolute Maximum Ratings" on page 58.
Power Sequencing Startup sequencing of the power supply voltages is not required. However, a power-down cycle must complete (OVDD and VDD are below +0.4V) before a new power-up cycle is started.
Table 10. Input Capacitance
Parameter Group 1 (2.5V SSTL I/O) Group 2 (3.3V LVTTL I/O) Group 3 (PCI I/O) Group 4 (Receivers) Group 5 (3.3V tolerant CMOS I/O) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 Maximum 2.5 2.1 2.5 0.9 2.4 Unit pF pF pF pF pF Notes
Table 11. Typical DC Power Supply Requirements
Frequency (MHz) 333 400 533 667 +1.5V Supply (VDD+AVDD+SAVDD) 1.00 1.09 1.28 1.93 +2.5V Supply (SVDD) 1.15 1.15 1.15 1.15 +3.3V Supply (OVDD) 0.04 0.04 0.04 0.04 Total 2.19 2.28 2.47 3.12 Unit W W W W Notes 1 1 1 1
Notes: 1. Typical Power is based on nominal voltage of VDD = +1.5V, TC = max. specified in Table 9 on page 59, while running Linux and a test application that exercises each core with representative traffic.
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Preliminary Data Sheet
Table 12. VDD Supply Power Dissipation
Frequency (MHz) 333 400 533 667 +1.4V 0.83 0.91 1.09 1.62 +1.5V 1.00 1.09 1.28 1.93 +1.6V 1.24 1.35 1.57 2.38 Unit W W W W Notes 1 1 1 1
Notes: 1. Power is based on VDD specified in the table and TC = max. specified in Table 9 on page 59, while running Linux and a test application that exercises each core with representative traffic.
Table 13. DC Power Supply Loads
Parameter VDD (1.5V) active operating current OVDD (3.3V) active operating current SVDD (2.5V) active operating current AVDD (1.5V) input current SAVDD (1.5V) active operating current Symbol IDD IODD ISDD IADD ISADD Typical 1250 10 460 3.2 6.05 Maximum 1900 100 600 5 10 Unit mA mA mA mA mA 1 1 Notes
Notes: 1. See "Absolute Maximum Ratings" on page 58 for filter recommendations. 2. The maximum current values listed above are not guaranteed to be the highest obtainable. These values are dependent on many factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case temperature, and the power supply voltages. Your specific application can produce significantly different results. VDD current and power are primarily dependent on the applications running and the use of internal chip functions (DMA, PCI, Ethernet, and so on). OVDD current and power are primarily dependent on the capacitive loading, frequency, and utilization of the external buses. 3. Typical current is estimated at 667MHz with VDD = +1.5V, OVDD = +3.3V, SVDD = +2.5V, and TC = +85C, while running Linux and a test application that exercises each core with representative traffic.. 4. Maximum current is estimated at 667MHz with VDD = +1.6V, OVDD = +3.6V, SVDD = +2.7V, and TC = +85C, and best-case process (which drives worst-case power), while running Linux and a test application that exercises each core with representative traffic.
Test Conditions Clock timing and switching characteristics are specified in accordance with operating conditions shown in the table "Recommended DC Operating Conditions." AC specifications are characterized with VDD = 1.5V, TC = +85 C and a 50pF test load as shown in the figure to the right.
Output Pin 50pF
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Preliminary Data Sheet
Table 14. Package Thermal Specifications
Thermal resistance values for the E-PBGA package are as follows:
Airflow ft/min (m/sec) 0 (0) Junction-to-ambient thermal resistance without heat sink Junction-to-ambient thermal resistance with heat sink 100 (0.51) 18.7 13.6 11.9 10.4 Resistance Value Junction-to-case thermal resistance 200 (1.02) 17.9 12.8 10.5 9.0 C/W C/W C/W C/W
Parameter
Symbol
Package
Unit
Notes
JA JA
E-PBGA TE-PBGA E-PBGA TE-PBGA
20.0 15.6 15.3 13.9
JC JB
E-PBGA TE-PBGA E-PBGA TE-PBGA
8.3 6.3 14.3 9.3
C/W C/W C/W C/W
Junction-to-board thermal resistance Notes:
1. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board. 2. TA = TC - Px CA, where TA is ambient temperature and P is power consumption. 3. 4. 5. 6.
TCMax = TJMax - PxJC, where TJMax is maximum junction temperature (+125C) and P is power consumption. The preceding equations assume that the chip is mounted on a board with at least one signal and two power planes. Values in the table were achieved with a JEDEC standard board: 114.5mm x 101.6mm x 1.6mm, 4 layers. Values for an attached heat sink were achieved with a 35mm x 35mm x 15mm unit (see Thermal Management below), attached with a 0.1mm thickness of adhesive having a thermal conductivity of 1.3 W/mK.
Thermal Management The following heat sinks were used in the above thermal analysis: ALPHA W35-15W (35mm x 35mm x15mm) ALPHA LPD35-15B (35mm x 35mm x15mm) The heat sinks are manufactured by: Alpha Novatech, Inc. (www.alphanovatech.com) 473 Sapena Court, #12 Santa Clara, CA 95054 Phone: 408-567-8082
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Preliminary Data Sheet
Table 15. Clocking Specifications
Symbol SysClk Input FC TC TCS TCH TCL Frequency Period Edge stability (cycle-to-cycle jitter) High time Low time 33.33 15 - 40% of nominal period 40% of nominal period 66.66 30 0.15 60% of nominal period 60% of nominal period MHz ns ns ns ns Parameter Min Max Units
Note: Input slew rate 1V/ns MemClkOut and PLB Clock FC TC TCH PLL VCO FC TC MAL Clock FC TC Frequency Period 45 12 83.33 22.2 MHz ns Frequency Period 600 0.7496 1334 1.66 MHz ns Frequency Period High time 100 7.5 45% of nominal period 133.33 10 55% of nominal period MHz ns ns
Figure 4. Timing Waveform
TCH TC
TCL
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Preliminary Data Sheet
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC440GR. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the PPC440GR the following conditions must be met: * The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the PPC440GR with one or more internal clocks at their maximum supported frequency, the SSCG can only lower the frequency. * The maximum frequency deviation cannot exceed -3%, and the modulation frequency cannot exceed 40kHz. In some cases, on-board PPC440GR peripherals impose more stringent requirements. * Use the Peripheral Bus Clock for logic that is synchronous to the peripheral bus since this clock tracks the modulation. * Use the DDR SDRAM MemClkOut since it also tracks the modulation.
Notes:
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the connected device is running at precise baud rates. 2. Ethernet operation is unaffected. 3. IIC operation is unaffected.
Important:
It is up to the system designer to ensure that any SSCG used with the PPC440GR meets the above requirements and does not adversely affect other aspects of the system.
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Preliminary Data Sheet
I/O Specifications
Table 16. Peripheral Interface Clock Timings
Parameter PCIClk input frequency (asynchronous mode) PCIClk period (asynchronous mode) PCIClk input high time PCIClk input low time EMCMDClk output frequency EMCMDClk period EMCMDClk output high time EMCMDClk output low time EMCTxClk input frequency MII(RMII) EMCTxClk period MII(RMII) EMCTxClk input high time EMCTxClk input low time EMCRxClk input frequency MII(RMII) EMCRxClk period MII(RMII) EMCRxClk input high time EMCRxClk input low time PerClk (and OPB Clock) output frequency (for ext. master or sync. slaves) PerClk period PerClk output high time PerClk output low time UARTSerClk input frequency UARTSerClk period UARTSerClk input high time UARTSerClk input low time TmrClk1 input frequency TmrClk1 period TmrClk1 input high time TmrClk1 input low time Notes: 1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB clock frequency is 66.66 MHz. 2. See Table 7 for information on the TmrClk2 signal. Min - 15 40% of nominal period 40% of nominal period - 400 160 160 2.5(5) 40(20) 35% of nominal period 35% of nominal period 2.5(5) 40(20) 35% of nominal period 35% of nominal period - 15 50% of nominal period 33% of nominal period - 2TOPB+2 TOPB+1 TOPB+1 - 10 40% of nominal period 40% of nominal period Max 66.66 - 60% of nominal period 60% of nominal period 2.5 - - - 25(50) 400(200) - - 25(50) 400(200) - - 66.66 - 66% of nominal period 50% of nominal period 1000/(2TOPB1+2ns) - - - 100 - 60% of nominal period 60% of nominal period Units MHz ns ns ns MHz ns ns ns MHz ns ns ns MHz ns ns ns MHz ns ns ns MHz ns ns ns MHz ns ns ns 1 1 1 1 2 Notes
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Preliminary Data Sheet
Figure 5. Input Setup and Hold Waveform
Clock
TIS min Inputs Valid
TIH min
Figure 6. Output Delay and Float Timing Waveform
Clock
TOV max Outputs TOH min
TOV max TOH min
TOV max TOH min
High (Drive) Float (High-Z) Low (Drive) Valid Valid
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Preliminary Data Sheet
Table 17. I/O Specifications--All Speeds (Sheet 1 of 2)
Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
Input (ns) Signal PCI Interface PCIAD31:00 PCIC3:0/BE3:0 PCIClk PCIDevSel PCIFrame PCIGnt0:5 PCIIDSel PCIINT PCIIRDY PCIPar PCIPErr PCIReq0:5 PCIReset PCISErr PCIStop PCITRDY Ethernet MII Interface EMCCD EMCCrS EMCDV EMCMDClk EMCMDIO EMCRxClk EMCRxD0:3 EMCRxErr EMCTxClk EMCTxD0:3 EMCTxEn EMCTxErr Ethernet RMII Interface EMC0CRSDV EMC0RxD0:1 EMC0RxErr EMC0TxD0:1 EMC1CRSDV EMC1RxD0:1 EMC1RxErr EMC1TxD0:1 EMCRefClk Ethernet SMII Interface EMC0RxD EMC0TxD EMC1RxD EMC1TxD EMCRefClk 1.5 n/a 1.5 n/a n/a 1 n/a 1 n/a n/a n/a 3.5 n/a 3.5 n/a n/a 0 n/a 0 n/a 5.1 5.1 5.1 5.1 5.1 6.8 6.8 6.8 6.8 6.8 EMCRefClk EMCRefClk EMCRefClk EMCRefClk 1 1 1 1 1, async 4 4 4 n/a 4 4 4 n/a n/a 2 2 2 n/a 2 2 2 n/a n/a n/a n/a n/a 12.5 n/a n/a n/a 12.5 n/a n/a n/a n/a 0 n/a n/a n/a 0 n/a 5.1 5.1 5.1 5.1 6.8 6.8 6.8 6.8 EMCRefClk EMCRefClk EMCRefClk 1 1 1 1, async 5.1 5.1 5.1 6.8 6.8 6.8 EMCRefClk EMCRefClk EMCRefClk 1 1 1 10 n/a 10 10 n/a n/a n/a n/a 10 n/a 10 10 n/a n/a n/a n/a 20 n/a n/a n/a n/a 20 20 20 0 n/a n/a n/a n/a 0 0 0 10 10 10 10 10 10 n/a n/a n/a n/a n/a n/a 5.1 5.1 5.1 5.1 5.1 5.1 5.1 5.1 na 5.1 5.1 5.1 6.8 6.8 6.8 6.8 6.8 6.8 6.8 6.8 na 6.8 6.8 6.8 EMCTxClk EMCTxClk EMCTxClk EMCRxClk EMCRxClk EMCMDClk 1, async 1 1, async 1 1 1, async 1 1 1 1, async 1, async 5 5 dc 5 5 n/a 5 n/a 5 5 5 5 n/a 5 5 5 0 0 dc 0 0 n/a 0 n/a 0 0 0 0 n/a 0 0 0 6 6 6 n/a 6 6 6 6 n/a n/a 6 6 6 2 2 2 n/a 2 2 2 2 n/a n/a 2 2 2 6 6 2 2 0.5 0.5 na 0.5 0.5 0.5 na 0.5 0.5 0.5 0.5 na na 0.5 0.5 0.5 1.5 1.5 na 1.5 1.5 1.5 na 1.5 1.5 1.5 1.5 na na 1.5 1.5 1.5 PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk async PCIClk PCIClk async Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) I/O H (minimum) I/O L (minimum) Clock Notes
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Table 17. I/O Specifications--All Speeds (Sheet 2 of 2)
Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
Input (ns) Signal Setup Time (TIS min) n/a n/a Hold Time (TIH min) n/a n/a Output (ns) Valid Delay (TOV max) 5 5 Hold Time (TOH min) 0 0 Output Current (mA) I/O H (minimum) 15.3 15.3 15.3 15.3 7 7 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 2 2 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 6 n/a 6 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 0 n/a 0 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 10.3 10.3 10.3 10.3 7.1 7.1 7.1 7.1 10.3 7.1 15.3 15.3 15.3 na na 10.3 na na na 10.3 na 10.3 na na na 15.3 na na na na na na 10.3 na na I/O L (minimum) 10.2 10.2 10.2 10.2 10.2 10.2 10.2 na na 7.1 na na na 7.1 na 7.1 na na na 10.2 na na na na na na 7.1 na na async async async async async async async async async async Clock Notes
Internal Peripheral Interface IIC0SClk IIC0SData IIC1SClk IIC1SData SCPClkOut SCPDI SCPDO UARTSerClk UARTn_Rx UARTn_Tx UARTn_DCD UARTn_DSR UARTn_CTS UARTn_DTR UARTn_RI UARTn_RTS Interrupts Interface IRQ0:9 JTAG Interface TCK TDI TDO TMS TRST System Interface SysClk TmrClk1:2 SysReset Halt SysErr TestEn DrvrInh1:2 RcvrInh GPIO00:63 PSROOut Trace Interface TrcClk TrcBS0:2 TrcES0:4 TrcTS0:6
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Table 18. I/O Specifications--333MHz to 533MHz
Notes: 1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.
Input (ns) Signal Setup Time (TIS min) n/a n/a 11.7 11.7 11.7 4 4 n/a 4 n/a 6 4 4 n/a n/a 4 n/a n/a 4 4 n/a 6 n/a n/a n/a 4 n/a n/a Hold Time (TIH min) n/a n/a 0.5 0.5 0.5 1 1 n/a 1 n/a 1 1 1 n/a n/a 1 n/a n/a 1 1 n/a 1 n/a n/a n/a 1 n/a n/a Output (ns) Valid Delay (TOV max) 10 10 n/a 10 10 7.2 6.5 6.5 7.2 6.5 n/a 6.5 6.5 6.5 6.5 n/a 6.0 6.5 n/a n/a n/a n/a 6.5 6.5 6.5 n/a 6.5 6.5 Hold Time (TOH min) 1 1 n/a 1 1 1.5 1.5 1.5 1.5 1.5 n/a 1.5 1.5 1.5 1.5 n/a 1.5 1.5 n/a n/a n/a n/a 1.5 1.5 1.5 n/a 1.5 1.5 Output Current (mA) I/O H (minimum) 5.1 15.3 na 5.1 15.3 15.3 15.3 10.3 15.3 15.3 15.3 15.3 15.3 7.1 7.1 n/a 15.3 7.1 na na 15.3 10.3 5.1 10.3 5.1 na 5.1 5.1 I/O L (minimum) 6.8 10.2 na 6.8 10.2 10.2 10.2 7.1 10.2 10.2 10.2 10.2 10.2 9.6 9.6 n/a 10.2 9.6 na na 10.2 7.1 6.8 7.1 6.8 na 6.8 6.8 PLB Clk PerClk 1 Clock Notes
External Slave Peripheral Interface DMAAck0:1 DMAAck2:3 DMAReq0:3 EOT0:1/TC0:1 EOT2:3/TC2:3 PerAddr02:31 PerBLast PerCS0:5 PerData00:15 PerOE PerReady PerR/W PerWBE0:1 BusReq ExtAck ExtReq ExtReset HoldAck HoldReq HoldPri PerClk PerErr NAND Flash Interface NFALE NFCE0:3 NFCLE NFRdyBusy NFREn NFWEn PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk
External Master Peripheral Interface
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DDR SDRAM I/O Specifications
The DDR SDRAM controller times its operation with internal PLB clock signals and generates MemClkOut0 from the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut0 is the same frequency as the PLB clock signal and is in phase with the PLB clock signal.
Note:
MemClkOut0 can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR programming register. In a typical system, users advance MemClkOut by 90. This depends on the specific application and requires a thorough understanding of the memory system in general (refer to the DDR SDRAM controller chapter in the PowerPC 440GR User's Manual).
In the following sections, the label MemClkOut0(0) refers to MemClkOut0 when it has not been phase-shifted, and MemClkOut0(90) refers to MemClkOut0 when it has been phase-advanced 90. Advancing MemClkOut0 by 90 creates a 3/4 cycle setup time and 1/4 cycle hold time for the address and control signals in relation to MemClkOut0(90). The rising edge of MemClkOut0(90) aligns with the first rising edge of the DQS signal. The following DDR data is generated by means of simulation and includes logic, driver, package RLC, and lengths. Values are calculated over best case and worst case processes with speed, temperature, and voltage as follows: Best Case = Fast process, -40C, +1.6V Worst Case = Slow process, +85C, +1.4V
Note: In all the following DDR tables and timing diagrams, minimum values are measured under best case conditions and maximum values are measured under worst case conditions.
The signals are terminated as indicated in the figure below for the DDR timing data in the following sections. Figure 7. DDR SDRAM Simulation Signal Termination Model
MemClkOut0 10pF 120 10pF MemClkOut0 VTT = VDD/2
PPC440GR
50 Addr/Ctrl/Data/DQS
30pF
Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data. It is not a recommended physical circuit design for this interface. An actual interface design will depend on many factors, including the type of memory used and the board layout.
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Table 19. DDR SDRAM Output Driver Specifications
Signal Path Write Data MemData00:07 MemData08:15 MemData16:23 MemData24:31 ECC0:7 DM0:8 MemClkOut0 MemAddr00:12 BA0:1 RAS CAS WE BankSel0:3 ClkEn0:3 DQS0:8 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 Output Current (mA) I/O H (maximum) I/O L (minimum)
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DDR SDRAM Write Operation
The following diagram illustrates the relationship among the signals involved with a DDR write operation. Figure 8. DDR SDRAM Write Cycle Timing
PLB Clk
MemClkOut0
MemClkOut0(90)
TSA Addr/Cmd TSK THA DQS TSD MemData THD TSD TDS TDS
THD
TSK = Delay from rising edge of MemClkOut0(0) to rising/falling edge of signal (skew) TSA = Setup time for address and command signals to MemClkOut0(90) THA = Hold time for address and command signals from MemClkOut0(90) TSD = Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ) THD = Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ) TDS = Delay from rising/falling edge of clock to the rising/falling edge of DQS
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Note:
The timing data in the following tables is based on simulation runs using Einstimer.
Table 20. I/O Timing--DDR SDRAM TDS
Notes: 1. All of the DQS signals are referenced to MemClkOut0(0). 2. Clock speed is 133MHz. 3. The TDS values in the table include 3/4 of a cycle at 133MHz (7.5ns x 0.75 = 5.625 ns). 4. To obtain adjusted values for lower clock frequencies, subtract 5.625 ns from the values in the table and add 3/4 of the cycle time for the lower clock frequency (TDS - 5.625 + 0.75TCYC).
Signal Name DQS0 DQS1 DQS2 DQS3 DQS8 TDS (ns) Minimum 5.76 5.78 5.82 5.79 5.75 Maximum 5.86 5.91 5.90 5.89 5.88
Table 21. I/O Timing--DDR SDRAM TSK, TSA, and THA
Notes: 1. Clock speed is 133MHz. TSK is referenced to MemClkOut0(0). TSA and THA are referenced to MemClkOut0(90). 2. To obtain adjusted TSA values for lower clock frequencies, use 3/4 of the cycle time for the lower clock frequency and subtract TSK maximum (0.75TCYC - TSKmax). 3. To obtain adjusted THA values for lower clock frequencies, use 1/4 of the cycle time for the lower clock frequency and add TSK minimum (0.25TCYC + TSKmin).
Signal Name MemAddr00:12 BA0:1 BankSel0:3 ClkEn0:3 CAS RAS WE TSK (ns) Minimum 0.11 0.07 0.05 0.07 0.05 0.05 0.08 Maximum 0.32 0.31 0.25 0.28 0.31 0.28 0.22 TSA (ns) Minimum 5.31 5.32 5.38 5.35 5.32 5.35 5.41 THA (ns) Minimum 1.99 1.95 1.93 1.95 1.93 1.93 1.96
Table 22. I/O Timing--DDR SDRAM TSD and THD
Notes: 1. TSD and THD are measured under worst case conditions. 2. Clock speed for the values in the table is 133MHz. 3. The time values in the table include 1/4 of a cycle at 166MHz (7.5ns x 0.25 = 1.875 ns). 4. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.875 ns from the values in the table and add 1/4 of the cycle time for the lower clock frequency (e.g., TSD - 1.875 + 0.25TCYC).
Signal Names MemData00:07, DM0 MemData08:15, DM1 MemData16:23, DM2 MemData24:31, DM3 ECC0:7, DM8 Reference Signal DQS0 DQS1 DQS2 DQS3 DQS8 TSD (ns) 1.795 1.775 1.745 1.765 1.685 THD (ns) 1.866 1.865 1.862 1.864 1.857
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DDR SDRAM Read Operation
The following examples of timing for DDR SDRAM read operations are based on the relationship between the incoming data and the PLB clock signal. Since the PLB clock cannot be directly observed, the delay of MemClkOut(0) relative to the PLB clock (TMD) is provided. The internal Read Clock signal, like MemClkOut0, is derived from the PLB clock and can be delayed relative to the PLB clock by programming the RDCT and RDCD fields in the SDRAM0_TR1 register. The delay can be programmed from 0 to 1/2 cycle in steps using RDCT. Setting RDCD results in a 1/2 cycle delay plus the value set in RDCT. The delay of Read Clock relative to the PLB clock (TRD) shown below assumes the programmable Read Clock delay is set to zero. Figure 9. DDR SDRAM MemClkOut0 and Read Clock Delay
PLB Clk
MemClkOut0(0) TMD TMDmin = 600ps TMDmax = 1100ps
Read Clock TRD TRDmin = 300ps TRDmax = 740ps
In operation, following the receipt of an address and read command from the PPC440GR, the SDRAM generates data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GR using a DQS signal that is delayed 1/4 of a cycle. In order to accommodate timing variations introduced by the system designs using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency. This adjustment requires programming the Read Clock delay and the selection of Stage 1, Stage 2, or Stage 3 data for sampling at RDSP.
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Figure 10. DDR SDRAM Read Data Path
Package pins Mux
D
RDSP
Q
Stage 1
D
Stage 2
Q D Q D
Stage 3
Q
ECC
FF
PLB bus
Data
FF, XL
C
FF
FF
C
C
C
DQS
1/4 Cycle Delay PLB Clock
Programmed Read Clock Delay
Read Select (SDRAM0_TR1)
FF Timing: TIS = Input setup time = 0.2ns TIH = Input hold time = 0.1ns TP = Propagation delay (D to Q or C to Q) = 0.4ns maximum
FF: Flip-Flop XL: Transparent Latch
Table 23. I/O Timing--DDR SDRAM TSIN and TDIN
Notes: 1. TSIN = Delay from DQS at package pin to C on Stage 1 FF. 2. TDIN = Delay from data at package pin to D on Stage 1 FF. 3. Clock speed for the values in the table is 133MHz. 4. The time values for TSIN include 1/4 of a cycle at 133MHz (7.5ns x 0.25 = 1.875 ns).
Signal Name DQS0 DQS1 DQS2 DQS3 DQS8 TSIN (ns) minimum 2.74 2.75 2.74 2.76 2.77 TSIN (ns) maximum 3.70 3.69 3.69 3.69 3.68 Signal Name MemData00:07 MemData08:15 MemData16:23 MemData24:31 ECC0:7 TDIN (ns) minimum 0.86 0.87 0.89 0.88 0.89 TDIN (ns) maximum 1.87 1.86 1.86 1.85 1.83
In the following examples, the data strobes (DQS) and the data are shown to be coincident. There is actually a slight skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal routing. It is recommended that the signal length for all of the eight DQS signals be matched.
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Example 1: If the data-to-PLB clock timing is as shown in the example below, then the read clock is not delayed and the Stage 1 data is sampled at (1). Except for small, low frequency memory systems with the memory located physically close to the PPC440GR, it is unlikely that Stage 1 data can be sampled. When the data comes later, it is necessary to sample Stage 2 or Stage 3 data. (see Examples 2 and 3). Another way to get the desired data-to-PLB timing to allow Stage 1 sampling is to buffer MemClkOut0 and skew it enough to guarantee the timing. In this example, TT is controlled and set by the software. Figure 11. DDR SDRAM Read Cycle Timing--Example 1
DQS at pin Data at pin D0 TSIN DQS Stage 1 C D1 D2 D3
Data in Stage 1 D TDIN
D0 TP TP High
D1
D2
D3
D0 D0 D1 D0 D0 D1 D2 D2
D2 D3 D2 D3
Data out Stage 1 Low
Data in at RDSP with no ECC
High Low TT
PLB Clock
High Data out RDSP Low
D0 D1
(1)
D2 D3
TSIN = Delay from DQS at package pin to C on Stage 1 FF. TP = Propagation delay through FFs TDIN = Delay from data at package pin to D on Stage 1 FF. TT = Propagation delay, Stage 1 input to RDSP input w/o ECC
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Example 2: In this example Read Clock is delayed almost 1/2 cycle. Without ECC, Stage 2 data can be sampled at (2). If ECC is enabled, Stage 3 data must be sampled (see Example 3). In this example, TT and TTE are controlled and set by the software. Figure 12. DDR SDRAM Read Cycle Timing--Example 2
DQS at pin Data at pin D0 TSIN D1 D2 D3
DQS Stage 1 C Data in Stage 1 D TDIN
D0
D1
D2
D3
TP High Data out Stage 1 Low D0 D1 D2 D3 D0 D2
PLB Clock Read Clock Delayed TP High Data out Stage 2 Low High Low TT TTE Data in at RDSP with ECC High Low D0 D1 D0 D1
(2)
D0 D1 D0 D1
D2 D3 D2 D3
Data in at RDSP without ECC
D2 D3 D2 D3
Data out at RDSP without ECC
High Low
TT = Propagation delay from Stage 2 input to RDSP input w/o ECC TTE = Propagation delay from Stage 2 input to RDSP input with ECC
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Example 3: In this example, ECC is enabled. This requires that Stage 3 data be sampled at (3). If ECC is disabled, the system will still work, but there will be more latency before the data is sampled into RDSP. In this example, TT and TTE are controlled and set by the software. Figure 13. DDR SDRAM Read Cycle Timing--Example 3
DQS at pin Data at pin D0 TSIN D1 D2 D3
DQS Stage 1 C Data in Stage 1 D TDIN
D0
D1
D2
D3
TP High Data out Stage 1 Low D0 D1 D2 D3 D0 D2
PLB Clock Read Clock Delayed TP High Data out Stage 2 Low High Low TTE Data in at RDSP with ECC High Low D0 D1 D0 D1
(3)
D0 D1 D0 D1
D2 D3 D2 D3
Data out Stage 3 with ECC
D2 D3 D2 D3
Data out RDSP with ECC
High Low
TT = Propagation delay from Stage 2 input to RDSP input w/o ECC TTE = Propagation delay from Stage 2 input to RDSP input with ECC
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Initialization
The PPC440GR provides the option for setting initial parameters based on default values or by reading them from a slave PROM attached to the IIC0 bus (see "Serial EEPROM" below). Some of the default values can be altered by strapping on external pins (see "Strapping" below).
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default initial conditions prior to PPC440GR start-up. The actual capture instant is the nearest reference clock edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. These pins are used for strap functions only during reset. Following reset they are used for normal functions. The signal names assigned to the pins for normal operation are shown in parentheses following the pin number. The following table lists the strapping pins along with their functions and strapping options:
Table 24. Strapping Pin Assignments
Ball Strapping Function Option R25 (UART0_DCD) 0 0 0 0 1 1 1 U26 (UART0_DSR) 0 0 1 1 0 1 0 V26 (UART0_CTS) 0 1 0 1 0 0 1
Serial device is disabled. Each of the six options (A- F) is a combination of boot source, boot-source width, and clock frequency specifications. Refer to the IIC Bootstrap Controller chapter in the PPC440GR Embedded Processor User's Manual for details.
A B C D E F
Serial device is enabled. The option being selected is the IIC0 slave address that will respond with strapping data. Note: If reading of configuration data from the serial device fails, the PPC440GR defaults to configuration X.
G (0xA8)
H (0xA4)
1
1
1
Serial EEPROM
During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device connected to the IIC0 port. At the de-assertion of reset, if the bootstrap controller is enabled, the PPC440GR sequentially reads 16B from the ROM device on the IIC0 port and sets the SDR0_SDSTP0, SDR0_SDSTP1, SDR0_SDSTP2 and SDR0_SDSTP3 registers accordingly. The initialization settings and their default values are covered in detail in the PowerPC 440GR User's Manual.
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Revision Log
Date 01/12/2005 01/27/2005 01/31/2005 03/03/2005 03/30/2005 04/18/2005 04/28/2005 05/09/2005 05/18/2005 06/06/2005 07/11/2005 07/20/2005 08/05/2005 09/21/2005 09/22/2005 10/06/2005 10/10/2005 1.10 1.11 1.12 1.08 1.09 Version Initial creation of document. Restore second DMA controller and make PVR and JTAG ID same as 440EP. Update DDR SDRAM timing. Update I/O definitions. Misc. corrections Remove 400MHz and 466MHz part numbers. Remove reference to USB end points. Update DDR SDRAM timing. Update reserved signals and add description of TmrClk2. Correct specs regarding the frequency range allowed for TmrClk2. Change description of TmrClk2. Add RoHS comliance statement and change maximum NAND Flash to 256MB. Misc. changes. Change solder ball size specification. Add power dissipation values for all supply voltages at the CPU speeds supported. Transfer applicable data (input capacitance, thermal performace, etc.) from 400EP data sheet. Misc. changes. Add 400Mhz CPU speed back into available PN list. Add default configuration X when bootstrap IIC read fails to Table 24. Add package nomenclature. Correct MemClkOut duty cycle. Correct description and move PerErr signal from master to slave. Change maximum VCO freqruency to 1334MHz. Add revision level B (1.1) part numbers and PVR numbers. Update power dissipation and add additional temperature data. Correct enable/disable specifications for PCI Gnt/Req signals. Contents of Modification
11/18/2005
1.13
02/16/2006 05/24/2006 07/19/2006
1.14 1.15 1.16
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Printed in the United States of America, August 4, 2006 The following are trademarks of AMCC Corporation in the United States, or other countries, or both: AMCC Other company, product, and service names may be trademarks or service marks of others.
Preliminary Edition (August 4, 2006)
This document contains information on a new product under development by AMCC. AMCC reserves the right to change or discontinue this product without notice. This document is a preliminary edition of the PowerPC 440GR data sheet. Make sure you are using the correct edition for the level of the product. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. The information contained in this document is subject to change or withdrawal at any time without notice and is being provided on an "AS IS" basis without warranty or indemnity of any kind, whether express or implied, including without limitation, the implied warranties of non-infringement, merchantability, or fitness for a particular purpose. Any products, services, or programs discussed in this document are sold or licensed under AMCC's standard terms and conditions, copies of which may be obtained from your local AMCC representative. Nothing in this document shall operate as an expressed or implied license or indemnity under the intellectual property rights of AMCC or third parties. Without limiting the generality of the foregoing, any performance data contained in this document was determined in a specific or controlled environment and not submitted to any formal AMCC test. Therefore, the results obtained in other operating environments may vary significantly. Under no circumstances will AMCC be liable for any damages whatsoever arising out of or resulting from any use of the document or the information contained herein.
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Preliminary Data Sheet
Applied Micro Circuits Corporation 215 Moffett Park Drive, Sunnyvale, CA 94089 Phone: (858) 450-9333 -- (800) 755-2622 -- Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products, its data sheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available data sheet. Please consult AMCC's Term and Conditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright (c) 2006 Applied Micro Circuits Corporation.
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